a well known problem in the manufacturing of electronic circuit boards is early failures which are referred to as infant failures. Statistically, the majority of the electrical devices that will fail in the first ten years will fail during the first year of operation. To reduce these failures and associated warranty cost, manufacturers perform burn-in tests. Such tests can eliminate the majority of the electrical devices that will fail during the first year of operation. During a burn-in test, the devices are subjected to elevated thermal or electrical operating conditions for a long period of time, typically, one to eight weeks, thereby simulating one year of operation under normal conditions.
The prior art has utilized different techniques to increase the reliability of the burn-in test. For example, U.S. Pat. No. 5,004,973 utilizes a bath of an inert liquid having a boiling point less than the desired temperature at which the electrical device is to be operated for testing purposes. This technique allows the device to be operated at the highest possible temperature without the device being destroyed. Since the temperature at which the device must be operated is often unique to a particular device, the technique of this latter patent does not work well on a circuit board having different types of devices. Further, the tests still require an extended amount of time.
It is also known in the prior art to vary the temperature at which a device is operating over a temperature range by changing the temperature of the air within a environmental test chamber. The range of air temperatures vary from the normal operating temperature of the device to its normal off-state temperature. Such a chamber is disclosed in U.S. Pat. No. 4,812,750. At the same time as the temperature is being varied, the power to the electronic components is turned on and off. It is a well known phenomenon that turning the power on and off does stress the component to a certain extent. In addition, U.S. Pat. No. 4,706,208 discloses that printed circuit boards can be tested by maintaining operational power on the printed circuit boards and cycling the environmental chamber through temperatures which simulate system testing, insulation, and normal use. It has also been the general practice in the electronic industry to place circuit boards containing electronic devices in a high temperature environmental test chamber and to vary the supply voltages to those circuit boards within the normal operating tolerances established for the devices on the printed circuit boards.
Whereas the prior art burn-in techniques have functioned well to produce products which have acceptable infant failure levels, the amount of time taken is normally measured in days or weeks. From a manufacturing point of view, these prior art burn-in periods are expensive because delays in producing the product, increased inventory cost, and added associated manufacturing expenses. Most importantly, however, prior art burn-in periods are not compatible with high velocity manufacturing and just-in-time (JIT) processes. The JIT process requires that the various parts needed to build a complex piece of electronic gear such as a modern telecommunications system arrive at the manufacturing plant almost simultaneously and that the complete electronic system is produced in a matter of a few days, often as short as four or five days. Since large amounts of time are required to assembly circuit boards, there is not sufficient time to use prior art burn-in times to reduce the infant failure levels. Further, burn-in of the individual electronic parts before they are assembled into printed circuit boards has shown only limited success because defective circuit boards are still found after assembly or after delivery to the customer.
Hence, there exists a long-felt need among electronic system manufacturers for a method which would reduce the time needed to perform burn-in or environmental stress screening.